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october 2010 ? 2008 fairchild semiconductor corporation www.fairchildsemi.com 74aup1t97 ? rev. 1.0.3 74aup1t97 ? tinylogic ? low power configurable gate with voltage-level translation 74aup1t97 tinylogic ? low power configurable gate with voltage-level translator features ? single supply voltage translator - 1.8v to 3.3v input at v cc =3.3v - 1.8v to 2.5v input at v cc =2.5v ? 2.3v to 3.6v v cc supply voltage operation ? 3.6v over-voltage tolerant i/o?s at v cc from 2.3v to 3.6v ? power-off high-impedance inputs and outputs ? low static power consumption - i cc =0.9a maximum ? low dynamic power consumption - c pd =2.7pf typical at 3.3v ? ultra-small micropak? packages description the 74aup1t97 is a universal configurable 2-input logic gate that provides single supply voltage level translation. this device is designed for applications with inputs switching levels that accept 1.8v low voltage cmos signals while operating from either a single 2.5v or 3.3v supply voltage. the 74aup1t97 is an ideal low power solution for mixed voltage signal applications especially for battery-powered portable applications. this product guarantees very low static and dynamic power consumption across entire voltage range. all inputs are implemented with hysteresis to allow for slower transition input signals and better switching noise immunity. the 74aup1t97 provides for multiple functions as determined by various configurations of the three inputs. the potential logic functions provided are mux, and, nand, or, and nor, inverter and buffer. refer to figures 3 to 9. ordering information part number top mark package packing method 74aup1t97l6x ah 6-lead micropak?, 1.0mm wide 5000 units on tape & reel 74AUP1T97FHX ah 6-lead, micropak 2?, 1x1mm body, .35mm pitch 5000 units on tape & reel
? 2008 fairchild semiconductor corporation www.fairchildsemi.com 74aup1t97 ? 1.0.3 2 74aup1t97 ? tinylogic ? low power configurable gate with voltage-level translator logic diagram 3 1 6 c b a 4 y figure 1. logic diagram (positive logic) pin configurations 1 b 2 gnd 3 6 5 4 a c v cc y figure 2. micropak? (top through view) pin definitions pin # name description 1 b data input 2 gnd ground 3 a data input 4 y output 5 v cc supply voltage 6 c data input
? 2008 fairchild semiconductor corporation www.fairchildsemi.com 74aup1t97 ? 1.0.3 3 74aup1t97 ? tinylogic ? low power configurable gate with voltage-level translator function table inputs 74aupit97 c b a y=output l l l l l l h l l h l h l h h h h l l l h l h h h h l l h h h h h = high logic level l = low logic level function selection table logic function connecti on configuration 2-to-1 mux figure 3 2-input and gate figure 4 2-input or gate with one inverted input figure 5 2-input nand gate with one inverted input figure 5 2-input and gate with one inverted input figure 6 2-input nor gate with one inverted input figure 6 2-input or gate figure 7 inverter figure 8 buffer figure 9
? 2008 fairchild semiconductor corporation www.fairchildsemi.com 74aup1t97 ? 1.0.3 4 74aup1t97 ? tinylogic ? low power configurable gate with voltage-level translator 74aup1t97 logic configurations figure 3 through figure 9 show the logical functions that can be implemented using the 74aup1t97. the diagrams show the demorgan?s equivalent logic duals for a given two-input function. the logical implementation is next to the board-level physical implementation of how the pins of the function should be connected. 1 2 3 6 5 4 b y c v cc b a c y a a gnd note: 1. when c is l, y=b. 2. when c is h, y=a. 1 2 3 6 5 4 a y c v cc c y a gnd figure 3. 2-to-1 mux figure 4. 2-input and gate 1 2 3 6 5 4 a y c v cc c y a c y a gnd c y b c y b 1 2 3 6 5 4 b y c v cc gnd figure 5. input or gate with one inverted input 2-input nand gate with one inverted input figure 6. 2-input and gate with one inverted input 2-input nor gate with one inverted input 1 2 3 6 5 4 b y c v cc c y b gnd 1 2 3 6 5 4 y c v cc y c gnd figure 7. 2-input or gate figure 8. inverter 1 2 3 6 5 4 y v cc y b gnd b figure 9. buffer
? 2008 fairchild semiconductor corporation www.fairchildsemi.com 74aup1t97 ? 1.0.3 5 74aup1t97 ? tinylogic ? low power configurable gate with voltage-level translator absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v cc supply voltage -0.5 4.6 v v in dc input voltage -0.5 4.6 v v out dc output voltage high or low state (3) -0.5 v cc + 0.5 v v cc =0v -0.5 4.6 i ik dc input diode current v in < 0v -50 ma i ok dc output diode current v out < 0v -50 ma v out > v cc +50 i oh / i ol dc output source / sink current 50 ma i o continuous output current 20 ma i cc or i gnd dc v cc or ground current per supply pin 50 ma t stg storage temperature range -65 +150 c t j junction temperature under bias +150 c t l junction lead temperature, soldering 10s +260 c p d power dissipation at +85c micropak-6 130 mw micropak2-6 120 esd human body model, jedec:jesd22-a114 5000+ v charged device model, jedec:jesd22-c101 2000 note: 3. i o absolute maximum rating must be observed. recommended operating conditions (4) the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ens ure optimal performance to the datasheet specifications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter conditions min. max. unit v cc supply voltage 2.3 3.6 v v in input voltage 0 3.6 v v out output voltage v cc =0v 0 3.6 v high or low state 0 v cc i oh /i ol output current v cc =3.0v to 3.6v 4.0 ma v cc =2.3v to 2.7v 3.1 t a operating temperature, free air -40 +85 c ja thermal resistance micropak-6 500 c/w micropak2-6 560 note: 4. unused inputs must be held high or low. they may not float.
? 2008 fairchild semiconductor corporation www.fairchildsemi.com 74aup1t97 ? 1.0.3 6 74aup1t97 ? tinylogic ? low power configurable gate with voltage-level translator dc electrical characteristics symbol parameter v cc conditions t a =+25c t a =-40 to +85c units min. max. min. max. v p positive threshold voltage 2.3v to 2.7v 0.60 1.10 0.60 1.10 v 3.0v to 3.6v 0.75 1.16 0.75 1.19 v n negative threshold voltage 2.3v to 2.7v 0.35 0.60 0.35 0.60 v 3.0v to 3.6v 0.50 0.85 0.50 0.85 v h hysteresis voltage 2.3v to 2.7v 0.23 0.60 0.10 0.60 v 3.0v to 3.6v 0.25 0.56 0.15 0.56 v oh high level output voltage 2.3v v cc 3.6v i oh =-20a v cc -0.1 v cc -0.1 v 2.3v i oh =-2.3ma 2.05 1.97 i oh =-3.1ma 1.90 1.85 3.0v i oh =-2.7ma 2.72 2.67 i oh =-4ma 2.60 2.55 v ol low level output voltage 2.3v v cc 3.6v i ol =20a 0.10 0.10 v 2.3v i ol =2.3ma 0.31 0.33 i ol =3.1ma 0.44 0.45 3.0v i ol =2.7ma 0.31 0.33 i ol =4.0ma 0.44 0.45 i in input leakage current 0v to 3.6v 0 v in 3.6 0.10 0.50 a i off power off leakage current 0v 0 (v in ,v o ) 3.6 0.10 0.50 a i off additional power off leakage current 0v to 0.2v v in or v o =0v to 3.6v 0.20 0.60 a i cc quiescent supply current 2.3v to 3.6v v in =v cc or gnd 0.50 0.90 a v cc v in 3.6v 0.90 i cc increase in i cc per input 2.3v to 2.7v one input at 0.3v or 1.1v, other inputs at 0 or v cc 4 a 3.0v to 3.6v one input at 0.45v or 1.2v, other inputs at 0 or v cc 12
? 2008 fairchild semiconductor corporation www.fairchildsemi.com 74aup1t97 ? 1.0.3 7 74aup1t97 ? tinylogic ? low power configurable gate with voltage-level translator ac electrical characteristics symbol parameter v cc conditions t a =+25c t a =-40 to +85c units figure min. typ. max. typ. max. t phl , t plh propagation delay 2.30v v cc 2.70v, v in =1.65v to 1.95v c l =5pf, r l =1m 1.1 3.7 5.5 1.1 6.8 ns figure 10 figure 11 2.30v v cc 2.70v, v in =2.30v to 2.70v 1.1 3.8 6.5 1.1 7.0 2.30v v cc 2.70v, v in =3.0v to 3.60v 1.1 3.9 6.0 1.1 6.5 3.00v v cc 3.60v, v in =1.65v to 1.95v 1.0 3.3 4.9 1.0 8.0 3.00v v cc 3.60v, v in =2.30v to 2.70v 1.0 3.2 4.6 1.0 5.8 3.00v v cc 3.60v, v in =3.00v to 3.60v 1.0 3.1 4.7 1.0 5.5 2.30v v cc 2.70v, v in =1.65v to 1.95v c l =10pf, r l =1m 1.3 4.1 6.5 1.0 7.9 2.30v v cc 2.70v, v in =2.30v to 2.70v 1.3 4.0 6.2 1.0 7.1 2.30v v cc 2.70v, v in =3.0v to 3.60v 1.3 3.7 5.7 1.0 6.5 3.00v v cc 3.60v, v in =1.65v to 1.95v 1.3 3.5 5.6 1.0 8.5 3.00v v cc 3.60v, v in =2.30v to 2.70v 1.3 3.4 5.3 1.0 6.1 3.00v v cc 3.60v, v in =3.00v to 3.60v 1.3 3.3 5.2 1.0 5.9 2.30v v cc 2.70v, v in =1.65v to 1.95v c l =15pf, r l =1m 1.5 4.6 6.9 1.0 8.7 2.30v v cc 2.70v, v in =2.30v to 2.70v 1.5 4.4 6.8 1.0 7.9 2.30v v cc 2.70v, v in =3.0v to 3.60v 1.5 4.2 6.3 1.0 7.4 3.00v v cc 3.60v, v in =1.65v to 1.95v 1.3 3.9 6.2 1.0 9.1 3.00v v cc 3.60v, v in =2.30v to 2.70v 1.3 3.8 5.6 1.0 6.8 3.00v v cc 3.60v, v in =3.00v to 3.60v 1.3 3.8 5.6 1.0 6.2 2.30v v cc 2.70v, v in =1.65v to 1.95v c l =30pf, r l =1m 1.3 4.2 7.9 1.3 8.5 2.30v v cc 2.70v, v in =2.30v to 2.70v 1.3 3.9 7.9 1.3 8.5 2.30v v cc 2.70v, v in =3.0v to 3.60v 1.0 3.7 7.3 1.0 8.9 3.00v v cc 3.60v, v in =1.65v to 1.95v 1.3 3.5 6.1 1.3 7.9 3.00v v cc 3.60v, v in =2.30v to 2.70v 1.1 3.0 5.9 1.1 6.8 3.00v v cc 3.60v, v in =3.00v to 3.60v 1.0 2.7 5.7 1.0 6.5 c in input capacitance 0 2.1 pf c out output capacitance 0 3.0 pf c pd power dissipation capacitance 2.30v v cc 2.70v 2.0 pf 3.00v v cc 3.60v 2.7
? 2008 fairchild semiconductor corporation www.fairchildsemi.com 74aup1t97 ? 1.0.3 8 74aup1t97 ? tinylogic ? low power configurable gate with voltage-level translator ac loadings and waveforms figure 10. ac test circuit figure 11. ac waveforms symbol v cc 3.3v 0.3v 2.5v 0.2v v mi v in /2 v in /2 v mo v cc /2 v cc /2
? 2008 fairchild semiconductor corporation www.fairchildsemi.com 74aup1t97 ? 1.0.3 9 74aup1t97 ? tinylogic ? low power configurable gate with voltage-level translator physical dimensions 2. dimensions are in millimeters 1. conforms to jedec standard m0-252 variation uaad 4. filename and revision: mac06arev4 notes: 3. drawing conforms to asme y14.5m-1994 top view recommened land pattern bottom view 1.45 1.00 a b 0.05 c 0.05 c 2x 2x 0.55max 0.05 c (0.49) (1) (0.75) (0.52) (0.30) 6x 1x 6x pin 1 detail a 0.075 x 45 chamfer 0.25 0.15 0.35 0.25 0.40 0.30 0.5 (0.05) 1.0 5x detail a pin 1 terminal 0.40 0.30 0.45 0.35 0.10 0.00 0.10 cba 0.05 c c 0.05 c 0.05 0.00 5x 5x 6x (0.13) 4x 6x pin 1 identifier (0.254) 5. pin one identifier is 2x length of any 5 other line in the mark code layout. figure 12. 6-lead, micropak?, 1.0mm wide package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and condition s, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . tape and reel specifications please visit fairchild semiconductor?s online packaging area for the most recent tape and reel specifications: http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf . package designator tape section cavity number cavity status cover type status l6x leader (start end) 125 (typical) empty sealed carrier 5000 filled sealed trailer (hub end) 75 (typical) empty sealed
? 2008 fairchild semiconductor corporation www.fairchildsemi.com 74aup1t97 ? 1.0.3 10 74aup1t97 ? tinylogic ? low power configurable gate with voltage-level translator physical dimensions 1.00 b. dimensions are in millimeters. c. dimensions and tolerances per asme y14.5m, 1994 notes: a. complies to jedec mo-252 standard 0.05 c a b 0.55max 0.05 c c 0.35 0.09 0.19 123 0.35 0.25 5x 6x detail a 0.60 (0.08) 4x (0.05) 6x 0.40 0.30 0.075x45 chamfer 5x 0.40 0.35 1x 0.45 6x 0.19 top view bottom view 0.66 0.10 cba .05 c 0.89 pin 1 0.05 c 2x 2x 1.00 d. landpattern recommendation is based on fsc e. drawing filename and revision: mgf06arev3 0.52 0.73 0.57 0.20 6x 1x 5x recommended land pattern for space constrained pcb detail a pin 1 lead scale: 2x alternative land pattern for universal application design. 0.90 min 250um 6 54 0.35 (0.08) 4x side view figure 13. 6-lead, micropak2?, 1x1mm body, .35mm pitch package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and condition s, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . tape and reel specifications please visit fairchild semiconductor?s online packaging area for the most recent tape and reel specifications: http://www.fairchildsemi.com/packaging/micropak2_6l_tr.pdf . package designator tape section cavity number cavity status cover type status fhx leader (start end) 125 (typical) empty sealed carrier 5000 filled sealed trailer (hub end) 75 (typical) empty sealed
? 2008 fairchild semiconductor corporation www.fairchildsemi.com 74aup1t97 ? 1.0.3 11 74aup1t97 ? tinylogic ? low power configurable gate with voltage-level translator

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